Integrated circuit fabrication may involve formation of high aspect ratio openings. Such openings may be utilized for fabrication of various circuit devices, such as, for example, capacitors. An advantage of forming the circuit devices within the high aspect ratio openings may be that the devices can then be made to occupy a relatively small footprint of a semiconductor wafer substrate. For instance, capacitors formed in high aspect ratio openings may have the same capacitive capacity as other capacitors, but may be formed to be very tall and thin so that individual capacitors occupy very little semiconductor real estate.
Difficulties may occur in forming tall, thin capacitors in that the capacitors may be prone to toppling. Various methods have been developed for avoiding toppling of tall, thin capacitors, with some of such methods comprising formation of a supporting lattice structure that assists in retaining the capacitors in a desired orientation. Some example lattice structures are described in U.S. Pat. Nos. 7,226,845 and 7,271,051; as well as in U.S. Publication Number 2006/0261440.
An example prior art process for forming openings extending through a lattice structure is described with reference to FIGS. 1 and 2.
FIG. 1 shows a semiconductor construction 10 at an early process stage of the process. The construction 10 comprises a semiconductor substrate, or base, 12. Substrate 12 can comprise, consist essentially of, or consist of, for example, monocrystalline silicon lightly-doped with background p-type dopant. The terms “semiconductive substrate” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
The semiconductor substrate 12 supports a pair of transistors 14 and 16. The transistor 14 comprises a gate 18 and a pair of source/drain regions 20 and 22. The source/drain regions extend into base 12, and may be either n-type majority doped or p-type majority doped. The gate 18 comprises a gate dielectric 24, a conductive segment 26, and an insulative cap 28. The gate dielectric may comprise, for example, silicon dioxide; the conductive segment 26 may comprise one or more of conductively-doped semiconductor material, metals, and metal-containing compounds; and the insulative capping layer may comprise, for example, silicon nitride.
A pair of sidewall spacers 30 extend along the opposing sidewalls of the gate 18, and such sidewall spacers may comprise, for example, silicon nitride.
The transistor 16 comprises a gate 32, source/drain region 22, and another source/drain region 34. The source/drain region 34 extends into base 12, and may be either n-type majority doped or p-type majority doped. The gate 32 comprises the gate dielectric 24, conductive segment 26, and insulative cap 28 discussed previously; and sidewall spacers 30 are along opposing sidewalls of the gate.
Isolation regions 19 extend into substrate 12 adjacent source/drain regions 20 and 34. The isolation regions may correspond to shallow trench isolation regions, and may contain silicon dioxide. The isolation regions may electrically isolate source/drain regions 20 and 34 from other circuitry (not shown).
An electrically insulative material 36 extends over and between the transistors 14 and 16. Electrically conductive pedestals 38, 40 and 42 extended through the electrically insulative material 36 to electrically connect with source/drain regions 20, 22 and 34, respectively.
A stack 44 is over the insulative material 36 and pedestals 38, 40 and 42. The stack comprises a first oxide-containing material 46, a first layer 48 of silicon nitride, a second oxide-containing material 50, and a second layer 52 of silicon nitride. The layers 48 and 52 ultimately become lattices to assist in retaining capacitors. The oxide-containing materials 46 and 50 may consist of silicon dioxide, or may consist of doped silicon dioxide (for instance, borophosphosilicate glass, phosphosilicate glass, fluorosilicate glass, etc.).
Transparent carbon 54 is over the second layer 52 of silicon nitride, deposited antireflective coating (DARC) 56 is over transparent carbon 54, bottom antireflective coating (BARC) 58 is over the DARC, and photolithographically-patterned photoresist 60 is over the BARC. The DARC may comprise, for example, silicon oxynitride; and the BARC may comprise any of various organic materials (i.e., may contain carbon).
The patterned photoresist defines a pair of openings 62 and 66.
FIG. 2 shows construction 10 after the openings 62 and 66 are extended through stack 44 with a plurality of etches, and after the transparent carbon 54 (FIG. 1), DARC 56 (FIG. 1), BARC 58 (FIG. 1) and photoresist 60 (FIG. 1) have been removed. The etches may comprise one more etches to extend through the BARC 58 and DARC 56 to the transparent carbon 54, followed by a dry etch utilizing O2/SO2 to penetrate through the transparent carbon. Such dry etch may also remove the photoresist 60 and the BARC 58. A subsequent etch may utilize CH2F2, CHF3 and O2 to penetrate the upper nitride layer 52, and to remove the DARC 56. Next, C4F6, O2 and Ar may be utilized to pass through the top oxide-containing material 50. An etch comprising CHF3, O2, CH2F2 and Ar may then be utilized to punch through the second nitride layer 48 and partially into the bottom oxide-containing material 46. Finally, C4F6, O2 and Ar may be utilized to remove a remaining portion of the bottom oxide-containing material 46 to form the shown openings. The transparent carbon 54 (FIG. 1) may be removed after the etching has passed through the top nitride layer 52 utilizing oxidation with O2, or any other suitable conditions.
A problem that may occur during the transfer of openings 62 and 66 into stack 44 is that bowing may occur in the top oxide-containing material 50, as is diagrammatically illustrated by curved regions 51 along sidewalls of material 50 within openings 62 and 66. Such bowing may result from any of various mechanisms, such as, for example, etching of material 50 during the etch through material 46, thinning of layer 52, etc.
Ultimately, capacitors are to be formed within openings 62 and 66 by depositing capacitor storage node material, capacitor dielectric material and capacitor plate material within the openings. The bowing within openings 62 and 66 complicates such capacitor fabrication.
It would be desired to develop new methods of capacitor fabrication which avoid the problems shown in FIG. 2.